* MARVELL MMP DMA controller

Marvell Peripheral DMA Controller
Used platforms: pxa688, pxa910, pxa3xx, etc

Required properties:
- compatible: Should be "marvell,pdma-1.0"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
		or one irq for pdma device

Optional properties:
- #dma-channels: Number of DMA channels supported by the controller (defaults
  to 32 when not specified)

"marvell,pdma-1.0"
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.

Examples:

/*
 * Each channel has specific irq
 * ICU parse out irq channel from ICU register,
 * while DMA controller may not able to distinguish the irq channel
 * Using this method, interrupt-parent is required as demuxer
 * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
 * 18~21 is ADMA irq
 */
pdma: dma-controller@d4000000 {
	      compatible = "marvell,pdma-1.0";
	      reg = <0xd4000000 0x10000>;
	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
	      interrupt-parent = <&intcmux32>;
	      #dma-channels = <16>;
      };

/*
 * One irq for all channels
 * Dmaengine driver (DMA controller) distinguish irq channel via
 * parsing internal register
 */
pdma: dma-controller@d4000000 {
	      compatible = "marvell,pdma-1.0";
	      reg = <0xd4000000 0x10000>;
	      interrupts = <47>;
	      #dma-channels = <16>;
      };


Marvell Two Channel DMA Controller used specifically for audio
Used platforms: pxa688, pxa910

Required properties:
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
		or one irq for dma device

"marvell,adma-1.0" used on pxa688
"marvell,pxa910-squ" used on pxa910

Examples:

/* each channel has specific irq */
adma0: dma-controller@d42a0800 {
	      compatible = "marvell,adma-1.0";
	      reg = <0xd42a0800 0x100>;
	      interrupts = <18 19>;
	      interrupt-parent = <&intcmux32>;
      };

/* One irq for all channels */
squ: dma-controller@d42a0800 {
	      compatible = "marvell,pxa910-squ";
	      reg = <0xd42a0800 0x100>;
	      interrupts = <46>;
      };
